1. Field of the Invention
The present invention relates to a bias voltage generator and a method of generating a bias voltage for a semiconductor memory device. More particularly, the invention relates to a bias voltage generator having increased sensing margin and improved resolution of a resistance dispersion curve, as well as a related method of generating a bias voltage within a semiconductor memory device.
2. Discussion of Related Art
An ideal semiconductor memory device would have high data storage capacity but would operate with low power consumption. Accordingly, considerable research and development effort has been expended to develop densely integrated, nonvolatile memory devices. Emerging examples of such memory devices include the phase-change random access memory (PRAM), the resistive random access memory (RRAM), and the magnetic random access memory (MRAM).
The PRAM uses one or more phase-change material(s) to store data in relation to a material phase state. Current phase-change materials include chalcogenides which have a resistance that varies with a phase state which may be altered by application of thermal energy. One such material is GexSbyTez (hereinafter, referred to as “GST”) which is an alloy of germanium (Ge), antimony (Sb) and tellurium (Te).
Phase-change materials capable of incorporation within a PRAM must be able to stably change phase states (e.g., between crystalline and amorphous states) very rapidly. In conventional PRAM devices, the phase-change material has high resistance in the amorphous state and low resistance in the crystalline state. As currently used in semiconductor memory devices, the amorphous state of the phase-change material may be defined as a ‘RESET’ state or data value of ‘1’, and the crystalline state may be defined as ‘SET’ state or a data value of ‘0’, or vice-versa.
Common memory cell types within a PRAM include a transistor structure or a diode structure. A memory cell having a transistor structure includes a phase-change material and an access transistor which are connected in series. A memory cell having a diode structure includes a phase-change material and a diode which are connected in series.
Compared to a PRAM memory cell having a transistor structure, a PRAM memory cell having a diode structure is capable of applying a relatively large write current which increases exponentially as a function of applied voltage. This greater write current capability allows relatively smaller diodes to be used in the implementation of an array of PRAM memory cells, thereby reducing the overall size of the constituent memory device. Therefore, it is expected that PRAM memory cells having a diode structure will be increasingly used in memory devices demanding a high integration density, a high operating speed, and low power consumption.
FIG. 1 illustrates a PRAM memory cell 50 having a diode structure. As shown in FIG. 1, PRAM memory cell 50 comprises a diode D and a variable resistor R. The variable resistor is implemented using one or more phase-change material(s).
Diode D forming memory cell 50 is connected between a word line WL and variable resistor R. That is, the cathode terminal of diode D is connected to the word line WL, and the anode terminal is connected to one end of the variable resistor R. The other end of the variable resistor R is connected to a bit line.
In a semiconductor memory device incorporating an array of memory cells like memory cell 50, a data write operation is performed using the reversible property of variable resistor R. That is, during a write operation applied to memory cell 50, electrical current is supplied through the bit line BL and the word line WL transitions to a low voltage level or a ground level. Then, a forward bias is applied to diode D, so that a current path is formed between the bit line BL and the word line WL. Then, the phase of variable resistor R is changed in relation to the current being applied and the application time of the current. Either ‘SET data’ indicated by a low resistance state or ‘RESET data’ indicated by a high resistance state may be stored in memory cell 50. In the working example, the SET data may be associated with a data value of ‘0’ and the RESET data may be associated with a data value of ‘1’, or vice versa.
A read operation may be used to determine a stored data value by distinguishing the state of memory cell 50. That is, the amount of current flowing through memory cell 50 is related to its resistance state. When RESET data is stored in memory cell 50, memory cell 50 has a high resistance value and the current passing through memory cell 50 is relatively small. However, when SET data is stored in memory cell 50, memory cell 50 has a low resistance value and the current passing through memory cell 50 is relatively large. Accordingly, data may be sensed according to the level of current passing through memory cell 50, or according to a voltage level change related to the level of current passing through memory cell 50.
The function of sensing data stored in a PRAM memory cell will be described in some additional detail with reference to an exemplary data read circuit for a PRAM device as illustrated in FIG. 2.
In FIG. 2, the data read circuit for a PRAM device comprises: a sense amplifier S/A, a current source 20, a clamping unit 10, a column selecting unit 40, and a cell array block 30.
The sense amplifier S/A may include a current sense amplifier or a voltage sense amplifier. The sense amplifier S/A senses data by comparing a voltage level at a sensing node Nsa, which is connected to a current path PA1 between the sensing node Nsa and a memory cell M, and a reference voltage level Vref. For example, when the voltage at sensing node Nsa applied to the input terminal of sense amplifier S/A is higher than the reference voltage Vref, a ‘HIGH’ data state is determined and output. When the voltage at sensing node Nsa is lower than the reference voltage Vref, a ‘LOW’ data state is determined and output at output terminal SAout. The ‘HIGH’ state indicates that memory cell M has a high resistance state, and the ‘LOW’ state indicates that memory cell M has the low resistance state.
Current source 20 is controlled by a bias voltage Vbias and supplies a sensing current Icell to the current path PA1. In the illustrated example, current source 20 includes a PMOS transistor PB which is connected to sensing node Nsa and a terminal Vsa to which a source voltage VDD or a high voltage VPP higher than the source voltage VDD is applied.
Clamping unit 10 includes clamp transistors NC controlled by a clamp signal Vclamp. The clamp transistors NC electrically connect any one memory cell from array block 30 which is selected from a plurality of cell array blocks forming array block 30 to sensing node Nsa of the sense amplifier S/A. Further, the clamp transistors NC maintain a specific voltage level so that the voltage of the bit line BL associated with the selected cell array block 30 is within the range of a threshold voltage Vth for the phase-change material. Therefore, the level of the clamp signal Vclamp is established consistent with the clamping function.
Column selecting unit 40 comprises a plurality of column selection transistors N0˜Nn switched by column selection signals Y0˜Yn. Column selection transistors N0˜Nn form current path PA1 between the bit line BL1 associated with the selected memory cell M in selected cell array block 30 and sensing node Nsa which is connected through clamp transistor NC. That is, the current path PA1 between sensing node Nsa of the sense amplifier S/A and the memory cell M is formed by a switching operation applied to the clamp transistors NC and the column selection transistors N0˜Nn. For example, when a column selection transistor N1 is turned ON by a column selection signal Y1, the current path PA1 is formed between the memory cell M and the sensing node Nsa.
Cell array block 30 includes memory cells which are disposed at the intersections of word lines WL0˜WLn and bit lines BL0˜BLn. Each memory cell may have a diode structure such as the one illustrated in FIG. 1.
The data read circuit performs the following to read data from the selected memory cell M in the cell array block 30.
When a read command, an address signal, and a clamp signal Vclamp are applied, the clamp signal Vclamp and the column selection signal Y1 are applied to form a current path PA1 between memory cell M and sensing node Nsa. At this time, the word line connected to memory cell M is maintained at ground level.
After current path PA1 is formed or at the same time at which current path PA1 is formed, a bias voltage Vbias is supplied to current source 20 to supply a current to the current path PA1. Accordingly, a sensing current (or penetrating current) Icell which depends on the resistance value of the memory cell M flows in the current path PA1.
The level of sensing current Icell flowing through current path PA1 varies in accordance with the data state of memory cell M (i.e., whether the memory cell M is in a reset data state or a set data state). When the memory cell M is in the reset data state, since it has a high resistance value, a small level of sensing current Icell flows through current path PA1. However, when the memory cell is in the set data state, it has a low resistance value and a relatively large level of sensing current Icell flows through the current path PA1. Accordingly, the voltage level of the sensing node Nsa which is connected to the input terminal of sense amplifier S/A is changed, and data sensing is performed by comparing the voltage level at the sensing node Nsa with the reference level Vref.
In the foregoing data read circuit, since the bias voltage Vbias controlling current source 20 supplying the sensing current Icell determines the amount of the current flowing through memory cell M and the voltage level at the sensing node Nsa, it must be carefully controlled. For example, when the selected memory cell M stores data indicated by a high resistance value (e.g., reset data or a data value of 1), the level of the bias voltage Vbias should be set so that the voltage level indicated at sensing node Nsa is higher than the reference voltage level Vref (e.g., one half the supply voltage (VDD/2)). However, when the selected memory cell M stores data indicated by a low resistance value (e.g., set data or a data value of 0), the level of the bias voltage Vbias should be set so that the voltage level indicated at sensing node Nsa is lower than the reference voltage level Vref. This does not mean that the bias voltage Vbias should be set to different levels depending on data state. Rather, this means that the bias voltage Vbias should be set to a fixed level for data sensing that meets the above conditions.
FIG. 3 is a bias voltage plot (G10) for resistance value points at which the voltage level at sensing node Nsa relative to the input bias voltage Vbias and the reference voltage level Vref applied in FIG. 2. The graph indicates SET and RESET states representing an exemplary resistance dispersion for set data and reset data.
In FIG. 3, the graphs of SET and RESET states showing the resistance dispersion for set and reset data are illustrated on a log scale. In the illustrated example, the set data graph SET has a resistance dispersion within a range of between 0 to 10KΩ, and the reset data graph RESET has a resistance dispersion in a range of between 50KΩ to 1 MΩ, or more. Therefore, as illustrated by the plot G10, the level of the bias voltage Vbias should be set such that the resistance value at a point at which the voltage level of the sensing node Nsa becomes the reference voltage level Vref falls within a range of between 10KΩ to 50KΩ. In this case, a bias voltage level margin range “S” is indicated between about 1.4 to 2.3V. This is a relatively small margin range and should be increased to improve performance of the memory cell.
In other PRAM implementations, each constituent memory cell is capable of storing multiple bits of data. Such implementations exacerbate the difficulties of providing a bias voltage definition capable of sensing multi-bit data with acceptable margins.
One example is described with reference to FIGS. 4 and 5. FIG. 4 is a graph containing a comparative plot (G10) showing a resistance value of the point at which the voltage level of the sensing node Nsa to the input bias voltage Vbias of FIG. 2 becomes the reference voltage level Vref. FIG. 5 is a distribution plot for multi-bit data states 00, 01, 10 and 11 by each bit, corresponding to the input bias voltage Vbias. Collectively, FIGS. 4 and 5 illustrate a memory cell capable of storing 2-bit data in four states 00, 01, 10 and 11, or first data 00, second data 01, third data 10, and fourth data 11.
In the working example, it is assumed that the first data 00 is indicated by a resistance dispersion of 0 to R1, second data 01 is indicated by a resistance dispersion of R2 to R3, third data 10 is indicated by a resistance dispersion of R4 to R5, and fourth data 11 is indicated by a resistance dispersion of R6 or more. It may be further assumed that the relation R1<R2<R3<R4<R5<R6 is satisfied.
As illustrated in FIGS. 4 and 5, the first data 00 is distributed across a first section I in which the level of the input bias voltage Vbias is lowest, second data 01 is distributed across a second section II in which the level of the input bias voltage is higher than the first section I, third data 10 is distributed across a third section III in which the level of the input bias voltage is higher than the second section II, and fourth data 11 is distributed across a fourth section IV in which the level of the input bias voltage is higher than the third section III.
A first sensing section S1 which is a level section of the bias voltage Vbias for sensing the first data 00 and the other data 01, 10 and 11 is positioned between the first section I and the second section II. When a voltage with a specific level within the first sensing section S1 is applied as the bias voltage Vbias, it is sensed whether the data stored in the memory cell is the first data 00, or any one of the second data 01, the third data 10, and the fourth data 11.
Further, a second sensing section S2 for sensing between the first and second data 00 and 01 or the third and fourth data 10 and 11 is positioned between the second section II and the third section III. When a voltage with a specific level within the second sensing section S2 is applied as the bias voltage Vbias, it is sensed whether the data stored in the memory cell is any one of the first and second data 00 and 01 or any one of the third and fourth data 10 and 11. When the sensing operation is performed by the bias voltage Vbias of the first sensing section S1 and the bias voltage Vbias of the second sensing section S2 and when the data stored in the memory cell is the first data 00 or the second data 01, it is sensed.
Next, a third sensing section S3 for distinguishing the first, second and third data 00, 01 and 10 from the fourth data 11 is positioned between the third section III and the fourth section IV. When a voltage with a specific level within the third sensing section S3 is applied as the bias voltage Vbias, it is sensed that whether the data stored in the memory cell is any one of the first, second and third data 00, 01 and 10 or the fourth data 11. When the data stored in the memory cell is the fourth data 11, the data is sensed by the sensing operation through the bias voltage Vbias of the third sensing section S3. However, when the data stored in the memory cell is the other data 00, 01 and/or 10, it is necessary to apply the bias voltage Vbias of the second sensing section S2 or/and the bias voltage Vbias of the first sensing section S1 for sensing the other data 00, 01 and/or 10.
In the graph G10 of the resistance value illustrated in FIG. 4, each of the first sensing section S1 and the second sensing section S2 has an adequate range, but the third sensing section S3 has a narrow range. The reason for result relates to the slope of the plot G10 for the resistance value as it increases from a proximate range of the third sensing section S3 by the threshold voltage of the PMOS transistor which is part of current source 20. This problem occurs when current source 20 is formed of the transistor. Although this problem does impact the determination between binary data states, when storing a greater number of data states per memory cell, a sensing section having a narrow range, like the third sensing section S3 in the illustrated example results. Moreover, the distribution range of the data in each section is not constant as is shown in FIG. 5. That is, the third section III where the third data 10 is distributed and the fourth section IV where the fourth data 11 is distributed are much narrower in range, compared to the first section I where the first data 00 is distributed and the second section II where the second data 01 is distributed. Moreover, since the third sensing section S3 which is the sensing section between the third section III and the fourth section IV is formed in a narrow range, the sensing margin is small.